Information about Researcher Poorvasha S
Researcher: Poorvasha S
Information
| Role | Researcher |
|---|---|
| First name | Poorvasha |
| Last name | S |
| Country | India |
| Academic title | Researcher |
| Organisation | Cognitive Design Technology Pvt Ltd |
| Thematic area/field | ST – Physical Sciences and Engineering / ST5 Materials |
| Key words | Semiconductor devices; wide band gap materials; nano-scale devices; simulation; CMOS technology |
More | |
| Short summary of activities and expertise | Dr Poorvasha S, Lead Application Engineer at Cognitive Design Technology Pvt Ltd, India, in collaboration with Silvaco Inc, designs, analyses, and optimises the characteristics of various semiconductor devices using the Technological Computer-Aided Design (TCAD) tool to achieve best-in-class device performances. Hold a PhD in Electronics Engineering from the Vellore Institute of Technology, India. PhD thesis, titled "Investigation of homo and heterojunction based double gate tunnel field-effect transistors for RF performance enhancement," was about developing a novel double gate (DG) tunnel field-effect transistor (TFET) in the nanoscale regime by device simulation using the TCAD tool to analyse and perform sensitivity analysis on various structural and doping parameters of the devices qualitatively, as well as investigating heterojunction-based TFETs to obtain the most important RF figure of merits (FOM). Research interest: Semiconductor devices have gained prominence in the IT market, allowing devices to become faster, more powerful, and less expensive. Furthermore, the rapidly expanding wireless market necessitates critical space in the semiconductor industry, which can be supported by RF and analog mixed-signal technologies. To incorporate the devices at the circuit level, a thorough understanding of their analog and RF behaviour is required, as well as an analysis of their behaviour at various dimensions to allow for eventual scaling. Would like to continue research on wideband gap-based devices for various RF parameters in order to pave the way for an exciting new frontier of low power switching that can operate at high frequencies. |
| Relevant publications and/or research/innovation products | ➢ Poorvasha S and Lakshmi B. Influence of structural and doping parameter variations on Si and Si1-x Gex double gate tunnel FETs: An analysis for RF performance enhancement. Pramana Journal of Physics, 91(2), 2018. https://doi.org/10.1007/s12043-018-1577-2 ➢ Poorvasha S and Lakshmi B. Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement. Journal of Semiconductors, 39, 054001-1-54001-11, 2018. 10.1088/1674-4926/39/5/054001 ➢ Poorvasha Shanmuganathan and Lakshmi Balasubramanian. Investigation of geometrical and doping parameter variations on GaSb/Si-based double gate Tunnel FETs: A qualitative and quantitative approach for RF performance enhancement. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 32(6), 2019. https://doi.org/10.1002/jnm.2633 ➢ Roop Narayan Goswami, Poorvasha S and Lakshmi B. Tunable work function in junctionless tunnel FETs for performance enhancement. Australian Journal of Electrical and Electronics Engineering, 15(3), 2018. https://doi.org/10.1080/1448837X.2018.1525173 ➢ Poorvasha S and Lakshmi B. Investigation of the device electrical parameters for homo and heterojunction based TFETs. Silicon 14, 2022. https://doi.org/10.1007/s12633-020-00934-z |
| Other relevant achievements | Conference Publications: ➢ Poorvasha S and Lakshmi B. Performance of asymmetric gate oxide on gate drain overlap in Si and Si1-xGex double gate tunnel FETs. 2nd IEEE International Conference on VLSI systems, architecture, technology and applications (VLSI SATA 2016), 10th-12th January 2016, Amrita School of Engineering, Bangalore, India. 10.1109/VLSI-SATA.2016.7593036 ➢ Poorvasha S and Lakshmi B. Analytical Approximation of Quantum mechanical tunneling and characterization of nano-scale heterojunction double gate tunnel FETs. International conference on manipulation, automation and robotics at small scales, 1st–5th July 2019, Helsinki, Finland. 10.1109/MARSS.2019.8860906 |
| Preferred Host Institution type | Public, Private, Academic, Non-academic, Research centre |
| Additional information | |
Contact | |
| poorvasha.s@gmail.com | |
| Phone number | 09790969776 |
| Website | https://scholar.google.com/citations?user=mlJcpAYAAAAJ&hl=en |
